Orchestrate for ASIC, SoC, and FPGA Designs
Orchestrate designs provide flexibility to allow easy configuration via mode control registers. This flexibility enables quick validation of your design and drives optimization of the design based on the results. The validation results can be analyzed to enhance the device performance for efficiency and reduce configuration requirements.
- Allowing any designer to quickly create efficient ASIC, SoC, or FPGA designs
- Reducing time to market
- Reducing front-end software tool costs
- Leveraging intellectual property (IP) module reuse
System Design Automation Components
Orchestrate SoC provides the foundation for next generation chip development. Orchestrate SoC enables ASIC, SoC, or FPGA development to generate flexible, synthesizable designs to accelerate your design cycles and reduce your time to market.
Players IP library contains the list of currently avaiable IP. This is available in addition to any IP that you have and wish to import. This IP library provides a marketplace for the industry to share and license their IP. This empowers designers to work on solving the next big thing rather than struggling with integration issues related to existing, mature technologies. This library provides open-source and licensed IP to the designer for inclusion in their project.View Players IP library »
Audition is a web-based tool for the new IP definition or existing IP import for use in rapid builds of new Orchestrate designs. Through easy to understand menus, the user is guided through the capture of IP interface information for even the most complicated IP blocks, ensuring operational compatibility with other IPs when used together in an SoC or FPGA design. Either Verilog or C/C++ code can be used for imported IP, and can be as parameterizable as the user desires. All interfacing to Orchestrate, such as Orchestrate specific wrappers, are handled automatically for the user. Audition is also a complete IP Management system. IP creators can specify priorities, handle version control, and create specific protections so that only certain engineers or projects can use the specific IP blocks.
- Quickly specify new IP functionality for independent internal or competitive outsourced development
- Easily import existing or new RTL or C/C++ models of IP for automated use by Orchestrate
- Ensure operational compatibility with other Audition-based IPs without modifying RTL or C/C++ code
- Collaborative web-based environment for specification, import, access, use, and verification
- Controlled view, use, and access protections that fully protect valuable IP source code
- Integrated test bench and simulation environment providing verification of IP following design integration
- Common point IP management for internal or external IP owners and users
Orchestrate is SDA!
Orchestrate SoC is the industry’s first automatic SoC creation system. Based on a patent-pending method of operation and hardware architecture, Orchestrate allows almost any engineer to quickly define, create, and verify new ASIC, SoC, and FPGA designs. Using our web-based, database driven software, engineers can import IP, select the necessary IP’s to create the system, produce the final system Verilog design, create the associated test bench, and simulate the entire design. Changes can easily be made through menu selections, making RTL editing unnecessary. Once the design is finalized, an RTL representation is produced which the engineer can take through their normal back-end flow.
- Reduce ASIC, SoC, and FPGA design time from months to days
- Allows engineers to quickly create efficient ASIC, SoC, and FPGA designs, no need to be an expert in design architectures
- Based on a highly efficient, Patent-Pending Hardware Architecture
- Integrated simulation environment, including the automatic creation of the system test bench.
- Easily import any existing IPs through the Audition product
- Automatic Verilog generation of the final design
- Fully synthesizable RTL and test benches, will work with all industry standard design flows
- Support for most of the popular emulator boards and emulation systems
Rehearse builds the complete IC design and corresponding Testbench and provides system level simulation and verification capabilities.
TCL based scripts can be written and executed to exercise the design and verify system behavior and functionality.